Database Paper Browser

Back to papers

Complex Event Detection at Wire Speed with FPGAs

Summary: FPGA-implemented complex event detection inserted between the NIC and CPU enables real-time CEP at gigabit wire speed. The design delivers constant, predictable latency independent of network load, packet size, or data distribution, enabling efficient hybrid CPU-FPGA stream processing. (summarized by gpt-5-nano on Feb 09 2026)

Paper ID
10115
Venue
VLDB
Year
2010
Pagerank
6.7561977e-05
Overall Rank
3,793 | 73.64%
DOI
-

Incoming Non-self Citations Over Time

Authors

Incoming Citations (Sorted by Pagerank)

Showing 14 of 14 citing papers.

Previous Page 1 / 1 Next

Outgoing Citations (Sorted by Pagerank)

Showing 7 of 7 cited papers.

Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.

Previous Page 1 / 1 Next

Semantically Similar Papers

Overall Rank Paper Year Venue Pagerank
5,179 FPGA-based Data Partitioning 2017 SIGMOD 5.6384436e-05
6,592 Complete Event Trend Detection in High-Rate Event Streams 2017 SIGMOD 4.9959015e-05
10,043 Accelerating Stream Processing Engines via Hardware Offloading 2026 SIGMOD 4.1905499e-05
4,456 Real-Time Multi-Pattern Detection over Event Streams 2019 SIGMOD 6.1644341e-05
259 High-Performance Complex Event Processing over Streams 2006 SIGMOD 0.00030155645
7,316 Efficient Adaptive Detection of Complex Event Patterns 2018 VLDB 4.7594979e-05
2,279 Streams on Wires — A Query Compiler for FPGAs 2009 VLDB 9.1249844e-05
4,383 Flexible Query Processor on FPGAs 2013 VLDB 6.2274297e-05
2,828 Plan-based Complex Event Detection across Distributed Sources 2008 VLDB 8.0545975e-05
948 Data Processing on FPGAs 2009 VLDB 0.0001510759