Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications
Summary: New access method uses microsecond-latency flash for random reads beyond DRAM, tackling CPU/IO bottlenecks. IO-issuance optimization plus stackless coroutines yield sub-10 ns per request and hide latency; BFS on large graphs nears DRAM at 88–141%. (summarized by gpt-5-nano on Feb 09 2026)
Incoming Non-self Citations Over Time
No non-self incoming citations found for this paper in this database.
Authors
- 1. Tomoya Suzuki
- 2. Kazuhiro Hiwada
- 3. Hirotsugu Kajihara
- 4. Shintaro Sano
- 5. Shuou Nomura
- 6. Tatsuo Shiozawa
Incoming Citations (Sorted by Pagerank)
Showing 1 of 1 citing papers.
| Rank | Citing Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 10,048 | Analysis and Evaluation of Using Microsecond-Latency Memory for In-Memory Indices and Caches in SSD-Based Key-Value Stores | 2026 | SIGMOD | 4.1945683e-05 |
Previous
Page 1 / 1
Next
Outgoing Citations (Sorted by Pagerank)
Showing 3 of 3 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
| Rank | Cited Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 4 | Pregel: A System for Large-Scale Graph Processing | 2010 | SIGMOD | 0.0019005923 |
| 3,193 | Exploiting Coroutines to Attack the "Killer Nanoseconds" | 2018 | VLDB | 7.4089674e-05 |
| 3,525 | Single Machine Graph Analytics on Massive Datasets Using Intel Optane DC Persistent Memory | 2020 | VLDB | 7.0080401e-05 |
Previous
Page 1 / 1
Next