CXL Memory Performance for In-Memory Data Processing
Summary: Analyzes PCIe-based cache-coherent CXL-attached memory for in-memory DBs, measuring interleaved access across multiple CXL devices for basic patterns, column scans and B+trees. Shows workload-aware column placement can store >80% of table data in CXL with ~85% throughput of local-only memory. (summarized by gpt-5-mini on Feb 09 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Marcel Weisgut
- 2. Daniel Ritter
- 3. Pinar Tözün
- 4. Lawrence Benson
- 5. Tilmann Rabl
Incoming Citations (Sorted by Pagerank)
Showing 2 of 2 citing papers.
| Rank | Citing Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 9,966 | Hash Joins Meet CXL: A Fresh Look | 2026 | CIDR | 4.1905499e-05 |
| 10,257 | SIDLE: Tree-structure Aware Indexes for CXL-based Heterogeneous Memory | 2026 | VLDB | 4.1905499e-05 |
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Outgoing Citations (Sorted by Pagerank)
Showing 26 of 26 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
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