Performance Evaluation of Extended Storage Architectures for Transaction Processing
Summary: Compares extended storage architectures (NVRAM, SSDs, disk caches) for transaction processing via simulation. Assesses log/database placement in non-volatile memory, an asynchronous write buffer, and multi-level caching under a debit–credit workload. (summarized by gpt-5-nano on Feb 09 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Erhard Rahm (University of Kaiserslautern)
BibTeX Citation
@inproceedings{rahm_sigmod92,
title = {{Performance Evaluation of Extended Storage Architectures for Transaction Processing}},
author = {Rahm, Erhard},
series = {{SIGMOD} '92},
booktitle = {Proceedings of the {ACM} {SIGMOD} International Conference on Management of Data},
publisher = {Association for Computing Machinery},
doi = {10.1145/130283.130329},
url = {https://dl.acm.org/doi/10.1145/130283.130329},
year = {1992}
}
Incoming Citations (Sorted by Pagerank)
Showing 2 of 2 citing papers.
| Rank | Citing Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 2,092 | Integrating Reliable Memory in Databases | 1997 | VLDB | 9.185168e-05 |
| 5,096 | Global Memory Management in Client-Server DBMS Architectures | 1992 | VLDB | 6.3653991e-05 |
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Outgoing Citations (Sorted by Pagerank)
Showing 5 of 5 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
| Rank | Cited Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 7 | Implementation Techniques For Main Memory Database Systems | 1984 | SIGMOD | 0.00083340894 |
| 133 | A Case for Redundant Arrays of Inexpensive Disks (RAID) | 1988 | SIGMOD | 0.00030370315 |
| 336 | THE 5 MINUTE RULE FOR TRADING MEMORY FOR DISC ACCESSES and THE 10 BYTE RULE FOR TRADING MEMORY FOR CPU TIME | 1987 | SIGMOD | 0.00020845451 |
| 1,711 | The Case For Safe RAM | 1989 | VLDB | 9.9498415e-05 |
| 2,630 | Parity Striping of Disc Arrays: Low-Cost Reliable Storage with Acceptable Throughput | 1990 | VLDB | 8.3249502e-05 |
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| 9 | 2,830 | An Analysis of Three Transaction Processing Architectures | 1988 | VLDB |
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