Efficient Hard Real-Time Transaction Processing - Unachievable in Software
Summary: Demonstrates throughput-tuned CPU transaction engines exhibit large latency tails (Cicada YCSB), making efficient hard‑real‑time guarantees infeasible in software. Advocates FPGA-based transaction processors for deterministic low latency, despite persistence/concurrency challenges. (summarized by gpt-5-mini on Feb 09 2026)
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Authors
- 1. Matheus A. Nerone (Centrum Wiskunde & Informatica)
- 2. Stefan Manegold (Centrum Wiskunde & Informatica)
- 3. Holger Pirk (Imperial College London)
BibTeX Citation
@inproceedings{nerone_cidr20,
address = {Amsterdam, Netherlands},
series = {{CIDR} '20},
title = {{Efficient Hard Real-Time Transaction Processing - Unachievable in Software}},
booktitle = {Proceedings of the {Conference} on {Innovative} {Data} {Systems} {Research}},
author = {Nerone, Matheus A. and Manegold, Stefan and Pirk, Holger},
year = {2020}
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Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
| Rank | Cited Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 760 | Cicada: Dependably Fast Multi-Core In-Memory Transactions | 2017 | SIGMOD | 0.0001425909 |
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