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Micro-architectural Analysis of In-memory OLTP

Summary: In-memory vs disk-based OLTP: micro-architecture is stall-dominated, with L1 instruction misses and LL cache misses driving most runtime. Aggressive compilation reduces instruction stalls but shifts bottlenecks to LL cache misses, IPC near one on modern CPUs. (summarized by gpt-5-nano on Feb 09 2026)

Paper ID
5107
Venue
SIGMOD
Year
2016
Pagerank
5.5937875e-05
Overall Rank
5,272 | 63.33%
DOI
10.1145/2882903.2882916

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