Optimistic Intra-Transaction Parallelism on Chip Multiprocessors

Summary: Speculative threads expose intra-transaction parallelism on chip multiprocessors while hiding parallelization from programmers and requiring only localized DBMS changes. The approach reduces TPC-C response time by 36–74% on a simulated four-processor CMP for three transactions. (summarized by gpt-5.6-luna on Jul 24 2026)

Paper ID: 9542
Venue: VLDB
Year: 2005
Pagerank: 5.093636e-05
Overall Rank: 12,759 | 12.47%
DOI: -

Incoming Non-self Citations Over Time

No non-self incoming citations found for this paper in this database.

Authors

1. Christopher B. Colohan (Carnegie Mellon University)
2. Anastassia Ailamaki (Carnegie Mellon University)
3. J. Gregory Steffan (University of Toronto)
4. Todd C. Mowry (Carnegie Mellon University; Intel)
5. Todd C. Mowry (Carnegie Mellon University; Intel)

BibTeX Citation

@article{colohan_vldb05,
        title = {{Optimistic Intra-Transaction Parallelism on Chip Multiprocessors}},
        author = {Colohan, Christopher B. and Ailamaki, Anastassia and Steffan, J. Gregory and Mowry, Todd C. and Mowry, Todd C.},
        journal = {PVLDB},
        series = {{VLDB} '05},
        year = {2005}
}

Incoming Citations (Sorted by Pagerank)

Showing 1 of 1 citing papers.

Rank	Citing Paper	Year	Venue	Pagerank
256	Data-Oriented Transaction Execution	2010	VLDB	0.00023172982

Outgoing Citations (Sorted by Pagerank)

Showing 2 of 2 cited papers.

Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.

Rank	Cited Paper	Year	Venue	Pagerank
64	Sagas	1987	SIGMOD	0.00038756588
6,982	Intra-Transaction Parallelism in the Mapping of an Object Model to a Relational Multi-Processor System	1996	VLDB	5.7303405e-05

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