RSR-core: A High-Performance Engine for Low-Bit Matrix-Vector Multiplication
Summary: RSR-core turns Redundant Segment Reduction for 1-/1.58-bit matrix-vector multiplication into optimized CPU/CUDA kernels, enabling practical binary/ternary LLM inference. HuggingFace integration delivers up to 62× CPU and 1.9× CUDA token-generation speedups. (summarized by gpt-5.6-luna on Aug 28 2026)
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Authors
- 1. Mohsen Dehghankar (University of Illinois Chicago)
- 2. Abolfazl Asudeh (University of Illinois Chicago)
BibTeX Citation
@article{dehghankar_vldb26,
title = {{RSR-core: A High-Performance Engine for Low-Bit Matrix-Vector Multiplication}},
author = {Dehghankar, Mohsen and Asudeh, Abolfazl},
journal = {PVLDB},
series = {{VLDB} '26},
volume = {19},
number = {12},
pages = {4726--4729},
doi = {10.14778/3827998.3828107},
url = {https://doi.org/10.14778/3827998.3828107},
year = {2026}
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| 4,715 | Maximum Inner Product is Query-Scaled Nearest Neighbor | 2025 | VLDB | 6.4554594e-05 |
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