The FastLanes Compression Layout: Decoding >100 Billion Integers per Second with Scalar Code
Summary: FastLanes redesigns LWC layouts with virtual-1024-bit interleaving and a unified transposed tuple order, exposing data parallelism across DICT, FOR, DELTA, and RLE. Scalar, auto-vectorizable code achieves >100B integer decodes/s across diverse CPUs. (summarized by gpt-5.6-luna on Jul 24 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Azim Afroozeh (Centrum Wiskunde & Informatica)
- 2. Peter Boncz (Centrum Wiskunde & Informatica)
BibTeX Citation
@article{afroozeh_vldb23,
title = {{The FastLanes Compression Layout: Decoding >100 Billion Integers per Second with Scalar Code}},
author = {Afroozeh, Azim and Boncz, Peter},
journal = {PVLDB},
series = {{VLDB} '23},
volume = {16},
number = {9},
pages = {2132--2144},
doi = {10.14778/3598581.3598587},
url = {https://doi.org/10.14778/3598581.3598587},
year = {2023}
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