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Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications

Summary: Introduces a flash access method that combines optimized I/O issuance with stackless-coroutine contexts, reducing per-request CPU overhead below 10 ns and hiding microsecond latency. Graph workloads on large flash-resident datasets achieve 88–141% of all-DRAM execution time. (summarized by gpt-5.6-luna on Jul 24 2026)

Paper ID
12509
Venue
VLDB
Year
2021
Pagerank
5.093636e-05
Overall Rank
11,693 | 19.78%
DOI
10.14778/3457390.3457397

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Authors

BibTeX Citation

@article{suzuki_vldb21,
        title = {{Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications}},
        author = {Suzuki, Tomoya and Hiwada, Kazuhiro and Kajihara, Hirotsugu and Sano, Shintaro and Nomura, Shuou and Shiozawa, Tatsuo},
        journal = {PVLDB},
        series = {{VLDB} '21},
        volume = {14},
        number = {8},
        pages = {1311--1324},
        doi = {10.14778/3457390.3457397},
        url = {https://doi.org/10.14778/3457390.3457397},
        year = {2021}
}

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