CXL Memory Performance for In-Memory Data Processing
Summary: Analyzes PCIe-based cache-coherent CXL-attached memory for in-memory DBs, measuring interleaved access across multiple CXL devices for basic patterns, column scans and B+trees. Shows workload-aware column placement can store >80% of table data in CXL with ~85% throughput of local-only memory. (summarized by gpt-5-mini on Feb 09 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Marcel Weisgut (Hasso Plattner Institute; University of Potsdam)
- 2. Daniel Ritter (SAP)
- 3. Pinar Tözün (IT University of Copenhagen)
- 4. Lawrence Benson (Technical University of Munich)
- 5. Tilmann Rabl (Hasso Plattner Institute; University of Potsdam)
BibTeX Citation
@article{weisgut_vldb25,
title = {{CXL Memory Performance for In-Memory Data Processing}},
author = {Weisgut, Marcel and Ritter, Daniel and Tözün, Pinar and Benson, Lawrence and Rabl, Tilmann},
journal = {PVLDB},
series = {{VLDB} '25},
volume = {18},
number = {9},
pages = {3119--3133},
doi = {10.14778/3746405.3746432},
url = {https://doi.org/10.14778/3746405.3746432},
year = {2025}
}Incoming Citations (Sorted by Pagerank)
Showing 2 of 2 citing papers.
| Rank | Citing Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 10,115 | Hash Joins Meet CXL: A Fresh Look | 2026 | CIDR | 5.093636e-05 |
| 10,545 | SIDLE: Tree-structure Aware Indexes for CXL-based Heterogeneous Memory | 2026 | VLDB | 5.093636e-05 |
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Outgoing Citations (Sorted by Pagerank)
Showing 26 of 26 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
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