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Is FPGA Useful for Hash Joins? Exploring Hash Joins on Coupled CPU-FPGA Architecture

Summary: Empirical exploration of hash-join acceleration on coupled CPU–FPGA (shared-memory) using OpenCL HLS and a roofline-guided analysis to identify optimal CPU/FPGA workload partitioning. Finds FPGA benefit constrained by system memory bandwidth and forecasts needed CPU–FPGA architectural features for DB workloads. (summarized by gpt-5-mini on Feb 09 2026)

Paper ID
363
Venue
CIDR
Year
2020
Pagerank
4.284797e-05
Overall Rank
9,785 | 31.93%
DOI
-

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Incoming Citations (Sorted by Pagerank)

Showing 1 of 1 citing papers.

Rank Citing Paper Year Venue Pagerank
8,417 The Case for Learned In-Memory Joins 2023 VLDB 4.5194164e-05
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Outgoing Citations (Sorted by Pagerank)

Showing 4 of 4 cited papers.

Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.

Rank Cited Paper Year Venue Pagerank
540 Design and Evaluation of Main Memory Hash Join Algorithms for Multi-core CPUs 2011 SIGMOD 0.0002063443
1,804 An Experimental Comparison of Thirteen Relational Equi-Joins in Main Memory 2016 SIGMOD 0.00010501185
5,178 FPGA-based Data Partitioning 2017 SIGMOD 5.6438393e-05
5,721 FPGA-based Multithreading for In-Memory Hash Joins 2015 CIDR 5.3525009e-05
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