Hardware-Oblivious SIMD Parallelism for In-Memory Column-Stores
Summary: Introduces Template Vector Library (TVL), a single‑source hardware‑oblivious abstraction for SIMD vectorization in in‑memory column-stores, decoupling operator code from concrete CPU SIMD ISAs. Enables portable high performance across diverse SIMD extensions and pure vector engines, and unlocks cross‑ISA optimizations that are hard or error‑prone with hardware-conscious implementations. (summarized by gpt-5-mini on Feb 09 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Annett Ungethüm (Technical University of Dresden)
- 2. Johannes Pietrzyk (Technical University of Dresden)
- 3. Patrick Damme (Technical University of Dresden)
- 4. Alexander Krause (Technical University of Dresden)
- 5. Dirk Habich (Technical University of Dresden)
- 6. Wolfgang Lehner (Technical University of Dresden)
- 7. Erich Focht (NEC Corporation)
BibTeX Citation
@inproceedings{ungethum_cidr20,
address = {Amsterdam, Netherlands},
series = {{CIDR} '20},
title = {{Hardware-Oblivious SIMD Parallelism for In-Memory Column-Stores}},
booktitle = {Proceedings of the {Conference} on {Innovative} {Data} {Systems} {Research}},
author = {Ungethüm, Annett and Pietrzyk, Johannes and Damme, Patrick and Krause, Alexander and Habich, Dirk and Lehner, Wolfgang and Focht, Erich},
year = {2020}
}
Incoming Citations (Sorted by Pagerank)
Showing 6 of 6 citing papers.
| Rank | Citing Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 3,592 | The FastLanes Compression Layout: Decoding >100 Billion Integers per Second with Scalar Code | 2023 | VLDB | 7.2774889e-05 |
| 6,665 | MorphStore: Analytical Query Engine with a Holistic Compression-Enabled Processing Model | 2020 | VLDB | 5.8089595e-05 |
| 7,160 | DAPHNE: An Open and Extensible System Infrastructure for Integrated Data Analysis Pipelines | 2022 | CIDR | 5.6855887e-05 |
| 8,443 | Analyzing Vectorized Hash Tables Across CPU Architectures | 2023 | VLDB | 5.4243766e-05 |
| 10,957 | Towards Designing Future-Proof Data Processing Systems | 2025 | VLDB | 5.093636e-05 |
| 11,116 | Program your (custom) SIMD instruction set on FPGA in C++ | 2024 | CIDR | 5.093636e-05 |
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Outgoing Citations (Sorted by Pagerank)
Showing 14 of 14 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
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