Efficient Hard Real-Time Transaction Processing - Unachievable in Software

Summary: Demonstrates throughput-tuned CPU transaction engines exhibit large latency tails (Cicada YCSB), making efficient hard‑real‑time guarantees infeasible in software. Advocates FPGA-based transaction processors for deterministic low latency, despite persistence/concurrency challenges. (summarized by gpt-5-mini on Feb 09 2026)

Paper ID: 381
Venue: CIDR
Year: 2020
Pagerank: 4.1945683e-05
Overall Rank: 11,550 | 19.65%
DOI: -

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Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.

Rank	Cited Paper	Year	Venue	Pagerank
1,069	Cicada: Dependably Fast Multi-Core In-Memory Transactions	2017	SIGMOD	0.00014319266

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