Micro-architectural Analysis of OLAP Systems on Persistent Memory
Summary: Microarchitectural study of six OLAP engines on byte-addressable persistent memory vs DRAM; systems behave divergently. PM increases data-cache stalls (to ~90% CPU cycles), causes up to 1.4x slowdown from intermediate writes via read–write asymmetry, and induces bandwidth saturation/interference among concurrent queries. (summarized by gpt-5-mini on Feb 09 2026)
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Authors
- 1. Jie Liang Ang (National University of Singapore)
- 2. Jefferson Chu (National University of Singapore)
- 3. Jiajun Liu (National University of Singapore)
- 4. Bingsheng He (National University of Singapore)
- 5. Hieu Le Trung (ByteDance)
- 6. Jiong He (ByteDance)
- 7. Qian Lin (ByteDance)
BibTeX Citation
@inproceedings{ang_cidr22,
address = {Amsterdam, Netherlands},
series = {{CIDR} '22},
title = {{Micro-architectural Analysis of OLAP Systems on Persistent Memory}},
booktitle = {Proceedings of the {Conference} on {Innovative} {Data} {Systems} {Research}},
author = {Ang, Jie Liang and Chu, Jefferson and Liu, Jiajun and He, Bingsheng and Le Trung, Hieu and He, Jiong and Lin, Qian},
year = {2022}
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