Optimistic Intra-Transaction Parallelism on Chip Multiprocessors
Summary: Speculative intra-transaction parallelism via lightweight threads on chip multiprocessors. Minimal, localized DBMS changes hide parallelization from programmers, delivering 36–74% response-time gains on a simulated 4-CPU CMP for three of five TPC-C transactions. (summarized by gpt-5-nano on Feb 09 2026)
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| Rank | Citing Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 338 | Data-Oriented Transaction Execution | 2010 | VLDB | 0.00026973858 |
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Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
| Rank | Cited Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 45 | Sagas | 1987 | SIGMOD | 0.00071800944 |
| 6,027 | Intra-Transaction Parallelism in the Mapping of an Object Model to a Relational Multi-Processor System | 1996 | VLDB | 5.2415551e-05 |
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