Database Paper Browser

Back to papers

Efficient Event Processing through Reconfigurable Hardware for Algorithmic Trading

Summary: FPGA-based event processing platform enabling line-rate, low-latency processing for algo trading. FPGA-ToPSS uses a reconfigurable hardware engine with expressive predicates to model complex strategies and autonomously execute trades in real time. (summarized by gpt-5-nano on Feb 09 2026)

Paper ID
9988
Venue
VLDB
Year
2010
Pagerank
6.6033808e-05
Overall Rank
3,945 | 72.56%
DOI
-

Incoming Non-self Citations Over Time

Authors

Incoming Citations (Sorted by Pagerank)

Showing 7 of 7 citing papers.

Previous Page 1 / 1 Next

Outgoing Citations (Sorted by Pagerank)

Showing 3 of 3 cited papers.

Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.

Rank Cited Paper Year Venue Pagerank
950 Data Processing on FPGAs 2009 VLDB 0.00015108484
2,054 Boosting XML Filtering with a Scalable FPGA-based Architecture 2009 CIDR 9.6725518e-05
2,272 Streams on Wires — A Query Compiler for FPGAs 2009 VLDB 9.1334837e-05
Previous Page 1 / 1 Next

Semantically Similar Papers