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Hardware Acceleration of Compression and Encryption in SAP HANA

Summary: FPGA-based accelerator offloads compression and encryption in SAP HANA, addressing I/O bottlenecks in an in-memory DB. SAP HANA traces show compression-then-encryption pipelines, multiple cipher modes, and FPGA-based decryption with CPU decompression, yielding tunable latency/throughput and storage-cost trade-offs. (summarized by gpt-5-nano on Feb 09 2026)

Paper ID
hc51ba139d992d139
Venue
VLDB
Year
2022
Pagerank
5.5845533e-05
Overall Rank
7,209 | 51.54%
DOI
10.14778/3554821.3554822

Incoming Non-self Citations Over Time

Authors

BibTeX Citation

@article{chiosa_vldb22,
        title = {{Hardware Acceleration of Compression and Encryption in SAP HANA}},
        author = {Chiosa, Monica and Maschi, Fabio and Müller, Ingo and Alonso, Gustavo and May, Norman},
        journal = {PVLDB},
        series = {{VLDB} '22},
        volume = {15},
        number = {12},
        pages = {3277--3291},
        doi = {10.14778/3554821.3554822},
        url = {https://doi.org/10.14778/3554821.3554822},
        year = {2022}
}

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