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Boosting XML Filtering with a Scalable FPGA-based Architecture

Summary: Pure-hardware, scalable FPGA architecture for XML pub-sub: compiles XPath subscriptions to regex-like FPGA circuits for massively parallel filtering. Adds in-FPGA stacks and co-located parsing to avoid host communication, yielding >10× throughput over software/mixed approaches. (summarized by gpt-5-mini on Feb 09 2026)

Paper ID
104
Venue
CIDR
Year
2009
Pagerank
9.6725518e-05
Overall Rank
2,054 | 85.72%
DOI
-

Incoming Non-self Citations Over Time

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Incoming Citations (Sorted by Pagerank)

Showing 6 of 6 citing papers.

Rank Citing Paper Year Venue Pagerank
950 Data Processing on FPGAs 2009 VLDB 0.00015108484
1,694 How Soccer Players Would do Stream Joins 2011 SIGMOD 0.00010893764
3,791 Complex Event Detection at Wire Speed with FPGAs 2010 VLDB 6.7624761e-05
3,945 Efficient Event Processing through Reconfigurable Hardware for Algorithmic Trading 2010 VLDB 6.6033808e-05
7,830 Scalable Structural Index Construction for JSON Analytics 2021 VLDB 4.6388763e-05
8,518 Glacier: A Query-to-Hardware Compiler 2010 SIGMOD 4.4943094e-05
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Outgoing Citations (Sorted by Pagerank)

Showing 9 of 9 cited papers.

Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.

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