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Complex Event Detection at Wire Speed with FPGAs

Summary: FPGA-implemented complex event detection inserted between the NIC and CPU enables real-time CEP at gigabit wire speed. The design delivers constant, predictable latency independent of network load, packet size, or data distribution, enabling efficient hybrid CPU-FPGA stream processing. (summarized by gpt-5-nano on Feb 09 2026)

Paper ID
10305
Venue
VLDB
Year
2010
Pagerank
7.1576479e-05
Overall Rank
3,744 | 74.32%
DOI
10.14778/1920841.1920926

Incoming Non-self Citations Over Time

Authors

BibTeX Citation

@article{woods_vldb10,
        title = {{Complex Event Detection at Wire Speed with FPGAs}},
        author = {Woods, Louis and Teubner, Jens and Alonso, Gustavo},
        journal = {PVLDB},
        series = {{VLDB} '10},
        volume = {3},
        number = {1},
        pages = {660--663},
        doi = {10.14778/1920841.1920926},
        url = {https://doi.org/10.14778/1920841.1920926},
        year = {2010}
}

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