Revisiting Co-Processing for Hash Joins on the Coupled CPU-GPU Architecture
Summary: Revisits hash joins on coupled CPU-GPU architectures, exploiting on-chip cache reuse and fine-grained co-processing with and without partitioning. Extends cost models to auto-guide design choices; on AMD APUs, achieves 53% CPU-only, 35% GPU-only, and 28% conventional co-processing gains. (summarized by gpt-5-nano on Feb 09 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Jiong He (Nanyang Technological University)
- 2. Mian Lu (Agency for Science, Technology and Research, Institute of High Performance Computing)
- 3. Bingsheng He (Nanyang Technological University)
BibTeX Citation
@article{he_vldb13,
title = {{Revisiting Co-Processing for Hash Joins on the Coupled CPU-GPU Architecture}},
author = {He, Jiong and Lu, Mian and He, Bingsheng},
journal = {PVLDB},
series = {{VLDB} '13},
volume = {6},
number = {10},
pages = {889--900},
doi = {10.14778/2536206.2536209},
url = {https://doi.org/10.14778/2536206.2536209},
year = {2013}
}
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