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Optimistic Data Parallelism for FPGA-Accelerated Sketching

Summary: Optimistic FPGA sketching: partition a single sketch into shared banks (vs. full replication) to cut critical resource use and enable larger summaries. Add merger units exploiting temporal locality to resolve skew-induced bank conflicts, yielding higher throughput and accuracy on a Xilinx U250 vs. CPU/GPU baselines. (summarized by gpt-5-mini on Feb 09 2026)

Paper ID
12981
Venue
VLDB
Year
2023
Pagerank
4.3684604e-05
Overall Rank
9,213 | 35.97%
DOI
10.14778/3579075.3579085

Incoming Non-self Citations Over Time

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Incoming Citations (Sorted by Pagerank)

Showing 2 of 2 citing papers.

Rank Citing Paper Year Venue Pagerank
9,458 DPDPU: Data Processing with DPUs 2025 CIDR 4.3344018e-05
10,516 SwiftSpatial: Spatial Joins on Modern Hardware 2025 SIGMOD 4.1905499e-05
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Outgoing Citations (Sorted by Pagerank)

Showing 7 of 7 cited papers.

Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.

Rank Cited Paper Year Venue Pagerank
398 Mergeable Summaries 2012 PODS 0.00024383201
778 Spectral Bloom Filters 2003 SIGMOD 0.00016729191
1,194 Join Size Estimation Subject to Filter Conditions 2015 VLDB 0.00013411666
1,394 Sketching Streams Through the Net: Distributed Approximate Query Tracking 2005 VLDB 0.00012218557
2,142 LSH Ensemble: Internet-Scale Domain Search 2016 VLDB 9.4461701e-05
7,163 SKT: A One-Pass Multi-Sketch Data Analytics Accelerator 2021 VLDB 4.808534e-05
8,715 Scotch: Generating FPGA-Accelerators for Sketching at Line Rate 2021 VLDB 4.4571724e-05
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