Analyzing Near-Network Hardware Acceleration with Co-Processing on DPUs
Summary: Empirical study of near-network hardware acceleration on PCIe DPUs, quantifying how performance depends on data types, task/query configurations, and DPU reconfiguration overhead. Micro-benchmarks of partial offloads and host–DPU co-processing reveal throughput vs reconfiguration trade-offs and offer practical integration guidance for data systems. (summarized by gpt-5-mini on Feb 09 2026)
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Authors
- 1. Dimitrios Giouroukis (Berlin Institute for the Foundations of Learning and Data; Technical University of Berlin)
- 2. Dwi P. A. Nugroho (Berlin Institute for the Foundations of Learning and Data; Technical University of Berlin)
- 3. Varun Pandey (Berlin Institute for the Foundations of Learning and Data; Technical University of Berlin)
- 4. Steffen Zeuch (Berlin Institute for the Foundations of Learning and Data; Technical University of Berlin)
- 5. Volker Markl (Berlin Institute for the Foundations of Learning and Data; German National Research Center for Information Technology; Technical University of Berlin)
BibTeX Citation
@article{giouroukis_vldb25,
title = {{Analyzing Near-Network Hardware Acceleration with Co-Processing on DPUs}},
author = {Giouroukis, Dimitrios and Nugroho, Dwi P. A. and Pandey, Varun and Zeuch, Steffen and Markl, Volker},
journal = {PVLDB},
series = {{VLDB} '25},
volume = {18},
number = {13},
pages = {5689--5702},
doi = {10.14778/3773731.3773743},
url = {https://doi.org/10.14778/3773731.3773743},
year = {2025}
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