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Discovery of Denial Constraints with Hardware Acceleration

Summary: DCArray accelerates denial-constraint discovery on FPGAs, replacing evidence-set materialization with prefix-tree Boolean patterns, pipelined parallel evaluation, and circuit-level minimality checks. It achieves up to 1560× speedup over DCFinder with predictable scaling, ultimately bounded by host–device I/O. (summarized by gpt-5.6-luna on Jul 26 2026)

Paper ID
7414
Venue
SIGMOD
Year
2026
Pagerank
5.093636e-05
Overall Rank
10,223 | 29.87%
DOI
10.1145/3802041

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BibTeX Citation

@inproceedings{filho_sigmod26,
        title = {{Discovery of Denial Constraints with Hardware Acceleration}},
        author = {Filho, Sergio Luiz Marques and de Almeida, Eduardo Cunha and Alves, Marco Antonio Zanata},
        series = {{SIGMOD} '26},
        booktitle = {Proceedings of the {ACM} {SIGMOD} International Conference on Management of Data},
        publisher = {Association for Computing Machinery},
        doi = {10.1145/3802041},
        url = {https://dl.acm.org/doi/10.1145/3802041},
        year = {2026}
}

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