Making Search Engines Faster by Lowering the Cost of Querying Business Rules Through FPGAs
Summary: Transforms BRMS rules into a non-deterministic finite automaton and maps it to FPGA to speed up MCT in airline search. Shows orders-of-magnitude speedups and potential 40% fewer machines, with on-prem and cloud validation. (summarized by gpt-5-nano on Feb 09 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Fabio Maschi (ETH Zurich)
- 2. Muhsen Owaida (ETH Zurich)
- 3. Gustavo Alonso (ETH Zurich)
- 4. Matteo Casalino (Amadeus)
- 5. Anthony Hock-Koon (Amadeus)
BibTeX Citation
@inproceedings{maschi_sigmod20,
title = {{Making Search Engines Faster by Lowering the Cost of Querying Business Rules Through FPGAs}},
author = {Maschi, Fabio and Owaida, Muhsen and Alonso, Gustavo and Casalino, Matteo and Hock-Koon, Anthony},
series = {{SIGMOD} '20},
booktitle = {Proceedings of the {ACM} {SIGMOD} International Conference on Management of Data},
publisher = {Association for Computing Machinery},
doi = {10.1145/3318464.3386133},
url = {https://dl.acm.org/doi/10.1145/3318464.3386133},
year = {2020}
}Incoming Citations (Sorted by Pagerank)
Showing 1 of 1 citing papers.
| Rank | Citing Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 10,223 | Discovery of Denial Constraints with Hardware Acceleration | 2026 | SIGMOD | 5.093636e-05 |
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Outgoing Citations (Sorted by Pagerank)
Showing 7 of 7 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
| Rank | Cited Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 229 | High-Performance Complex Event Processing over Streams | 2006 | SIGMOD | 0.00023927582 |
| 3,744 | Complex Event Detection at Wire Speed with FPGAs | 2010 | VLDB | 7.1576479e-05 |
| 3,946 | Real-Time Multi-Pattern Detection over Event Streams | 2019 | SIGMOD | 7.0046969e-05 |
| 4,483 | Accelerating Raw Data Analysis with the ACCORDA Software and Hardware Architecture | 2019 | VLDB | 6.6724044e-05 |
| 7,170 | Lowering the Latency of Data Processing Pipelines Through FPGA based Hardware Acceleration | 2020 | VLDB | 5.6840081e-05 |
| 7,852 | Indexing and Selecting Hierarchical Business Logic | 2015 | VLDB | 5.5313703e-05 |
| 8,199 | Accelerating Pattern Matching Queries in Hybrid CPU-FPGA Architectures | 2017 | SIGMOD | 5.4686907e-05 |
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Semantically Similar Papers
| # | Overall Rank | Paper | Year | Venue |
|---|---|---|---|---|
| 1 | 5,515 | FPGA-based Multithreading for In-Memory Hash Joins | 2015 | CIDR |
| 2 | 3,744 | Complex Event Detection at Wire Speed with FPGAs | 2010 | VLDB |
| 3 | 2,181 | Streams on Wires — A Query Compiler for FPGAs | 2009 | VLDB |
| 4 | 922 | Data Processing on FPGAs | 2009 | VLDB |
| 5 | 4,313 | Flexible Query Processor on FPGAs | 2013 | VLDB |
| 6 | 3,804 | Skeleton Automata for FPGAs: Reconfiguring without Reconstructing | 2012 | SIGMOD |
| 7 | 9,776 | Fast Graph Vector Search via Hardware Acceleration and Delayed-Synchronization Traversal | 2025 | VLDB |
| 8 | 8,199 | Accelerating Pattern Matching Queries in Hybrid CPU-FPGA Architectures | 2017 | SIGMOD |
| 9 | 10,223 | Discovery of Denial Constraints with Hardware Acceleration | 2026 | SIGMOD |
| 10 | 7,170 | Lowering the Latency of Data Processing Pipelines Through FPGA based Hardware Acceleration | 2020 | VLDB |