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Lowering the Latency of Data Processing Pipelines Through FPGA based Hardware Acceleration

Summary: An FPGA-based decision-tree ensemble accelerator targets search scoring, reducing data movement and enabling pipeline-stage fusion. Evaluated on Amazon F1, it delivers compact, massively parallel scoring and up to two orders-of-magnitude speedup over CPUs. (summarized by gpt-5.6-luna on Jul 24 2026)

Paper ID
12456
Venue
VLDB
Year
2020
Pagerank
5.6840081e-05
Overall Rank
7,170 | 50.81%
DOI
10.14778/3357377.3357383

Incoming Non-self Citations Over Time

Authors

BibTeX Citation

@article{owaida_vldb20,
        title = {{Lowering the Latency of Data Processing Pipelines Through FPGA based Hardware Acceleration}},
        author = {Owaida, Muhsen and Alonso, Gustavo and Fogliarini, Laura and Hock-Koon, Anthony and Melet, Pierre-Etienne},
        journal = {PVLDB},
        series = {{VLDB} '20},
        volume = {13},
        number = {1},
        pages = {71--84},
        doi = {10.14778/3357377.3357383},
        url = {https://doi.org/10.14778/3357377.3357383},
        year = {2020}
}

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