Faster Set Intersection with SIMD instructions by Reducing Branch Mispredictions
Summary: Introduces a branch-misprediction-resilient SIMD algorithm for intersecting sorted arrays, comparing blocks of elements and advancing pointers multiple positions. It requires no preprocessing and beats gcc’s std::set_intersection by up to 5.2× on Xeon/POWER7+. (summarized by gpt-5.6-luna on Jul 24 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Hiroshi Inoue (IBM)
- 2. Moriyoshi Ohara (IBM)
- 3. Kenjiro Taura (University of Tokyo)
BibTeX Citation
@article{inoue_vldb15,
title = {{Faster Set Intersection with SIMD instructions by Reducing Branch Mispredictions}},
author = {Inoue, Hiroshi and Ohara, Moriyoshi and Taura, Kenjiro},
journal = {PVLDB},
series = {{VLDB} '15},
volume = {8},
number = {3},
pages = {293--304},
doi = {10.14778/2735508.2735516},
url = {https://doi.org/10.14778/2735508.2735516},
year = {2015}
}
Incoming Citations (Sorted by Pagerank)
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Outgoing Citations (Sorted by Pagerank)
Showing 5 of 5 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
| Rank | Cited Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 287 | Implementing Database Operations Using SIMD Instructions | 2002 | SIGMOD | 0.00022001327 |
| 723 | Efficient Implementation of Sorting on Multi-Core SIMD CPU Architecture | 2008 | VLDB | 0.00014507399 |
| 1,653 | Efficient Parallel Lists Intersection and Index Compression Algorithms using Graphics Processing Units | 2011 | VLDB | 9.969498e-05 |
| 1,730 | Improving the Performance of List Intersection | 2009 | VLDB | 9.7686642e-05 |
| 2,120 | Fast Set Intersection in Memory | 2011 | VLDB | 9.0077549e-05 |
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