Efficient Implementation of Sorting on Multi-Core SIMD CPU Architecture
Summary: SIMD-optimized MergeSort with cache-efficient multiway merging achieves 3.3× scalar speedup and sorts 64M floats in <0.5s on a 4-core CPU. Analytical and cycle-accurate studies show scalability across SIMD widths and 32+ cores. (summarized by gpt-5.6-luna on Jul 24 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Jatin Chhugani (Intel)
- 2. Anthony D. Nguyen (Intel)
- 3. Victor W. Lee (Intel)
- 4. William Macy (Intel)
- 5. Mostafa Hagog (Intel)
- 6. Yen-Kuang Chen (Intel)
- 7. Akram Baransi (Intel)
- 8. Sanjeev Kumar (Intel)
- 9. Pradeep Dubey (Intel)
BibTeX Citation
@article{chhugani_vldb08,
title = {{Efficient Implementation of Sorting on Multi-Core SIMD CPU Architecture}},
author = {Chhugani, Jatin and Nguyen, Anthony D. and Lee, Victor W. and Macy, William and Hagog, Mostafa and Chen, Yen-Kuang and Baransi, Akram and Kumar, Sanjeev and Dubey, Pradeep},
journal = {PVLDB},
series = {{VLDB} '08},
volume = {1},
number = {1},
pages = {1313--1324},
doi = {10.14778/1454159.1454171},
url = {https://doi.org/10.14778/1454159.1454171},
year = {2008}
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Showing 2 of 2 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
| Rank | Cited Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 304 | GPUTeraSort: High Performance Graphics Co-processor Sorting for Large Database Management | 2006 | SIGMOD | 0.00021604795 |
| 2,161 | CellSort: High Performance Sorting on the Cell Processor | 2007 | VLDB | 8.9357193e-05 |
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