Optimistic Data Parallelism for FPGA-Accelerated Sketching
Summary: Introduces optimistic FPGA sketching: shared banked state replaces fully replicated per-lane sketches, cutting critical resource use proportionally to parallelism. Temporal-locality mergers mitigate skew-induced bank conflicts, delivering higher throughput and larger, more accurate sketches. (summarized by gpt-5.6-luna on Jul 24 2026)
Incoming Non-self Citations Over Time
Authors
- 1. Martin Kiefer (Technical University of Berlin)
- 2. Ilias Poulakis (Technical University of Berlin)
- 3. Eleni Tzirita Zacharatou (IT University of Copenhagen)
- 4. Volker Markl (German National Research Center for Information Technology; Technical University of Berlin)
BibTeX Citation
@article{kiefer_vldb23,
title = {{Optimistic Data Parallelism for FPGA-Accelerated Sketching}},
author = {Kiefer, Martin and Poulakis, Ilias and Zacharatou, Eleni Tzirita and Markl, Volker},
journal = {PVLDB},
series = {{VLDB} '23},
volume = {16},
number = {5},
pages = {1113--1125},
doi = {10.14778/3579075.3579085},
url = {https://doi.org/10.14778/3579075.3579085},
year = {2023}
}
Incoming Citations (Sorted by Pagerank)
Showing 3 of 3 citing papers.
| Rank | Citing Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 9,511 | DPDPU: Data Processing with DPUs | 2025 | CIDR | 5.25736e-05 |
| 9,544 | SwiftSpatial: Spatial Joins on Modern Hardware | 2025 | SIGMOD | 5.2528121e-05 |
| 10,295 | Sublime: Sublinear Error & Space for Unbounded Skewed Streams | 2026 | SIGMOD | 5.093636e-05 |
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Outgoing Citations (Sorted by Pagerank)
Showing 7 of 7 cited papers.
Citations counted here include only citations to other VLDB/SIGMOD/CIDR/PODS papers in this database.
| Rank | Cited Paper | Year | Venue | Pagerank |
|---|---|---|---|---|
| 451 | Mergeable Summaries | 2012 | PODS | 0.00018151445 |
| 737 | Join Size Estimation Subject to Filter Conditions | 2015 | VLDB | 0.00014490983 |
| 862 | Spectral Bloom Filters | 2003 | SIGMOD | 0.00013532857 |
| 1,045 | Sketching Streams Through the Net: Distributed Approximate Query Tracking | 2005 | VLDB | 0.00012440928 |
| 1,495 | LSH Ensemble: Internet-Scale Domain Search | 2016 | VLDB | 0.00010571481 |
| 7,069 | SKT: A One-Pass Multi-Sketch Data Analytics Accelerator | 2021 | VLDB | 5.7117595e-05 |
| 8,878 | Scotch: Generating FPGA-Accelerators for Sketching at Line Rate | 2021 | VLDB | 5.3532614e-05 |
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Semantically Similar Papers
| # | Overall Rank | Paper | Year | Venue |
|---|---|---|---|---|
| 1 | 7,170 | Lowering the Latency of Data Processing Pipelines Through FPGA based Hardware Acceleration | 2020 | VLDB |
| 2 | 10,026 | DASH: Asynchronous Hardware Data Processing Services | 2023 | CIDR |
| 3 | 11,116 | Program your (custom) SIMD instruction set on FPGA in C++ | 2024 | CIDR |
| 4 | 1,294 | Augmented Sketch: Faster and More Accurate Stream Processing | 2016 | SIGMOD |
| 5 | 5,515 | FPGA-based Multithreading for In-Memory Hash Joins | 2015 | CIDR |
| 6 | 9,939 | Is FPGA Useful for Hash Joins? Exploring Hash Joins on Coupled CPU-FPGA Architecture | 2020 | CIDR |
| 7 | 922 | Data Processing on FPGAs | 2009 | VLDB |
| 8 | 7,069 | SKT: A One-Pass Multi-Sketch Data Analytics Accelerator | 2021 | VLDB |
| 9 | 8,878 | Scotch: Generating FPGA-Accelerators for Sketching at Line Rate | 2021 | VLDB |
| 10 | 4,840 | FPGA-based Data Partitioning | 2017 | SIGMOD |