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Hardware-Oblivious SIMD Parallelism for In-Memory Column-Stores

Summary: Introduces Template Vector Library (TVL), a single‑source hardware‑oblivious abstraction for SIMD vectorization in in‑memory column-stores, decoupling operator code from concrete CPU SIMD ISAs. Enables portable high performance across diverse SIMD extensions and pure vector engines, and unlocks cross‑ISA optimizations that are hard or error‑prone with hardware-conscious implementations. (summarized by gpt-5-mini on Feb 09 2026)

Paper ID
364
Venue
CIDR
Year
2020
Pagerank
4.6445165e-05
Overall Rank
7,811 | 45.67%
DOI
-

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